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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. june 2004 copyright ? intel corporation, 2004 order number: 270419-00 8 80c31bh/80c51bh/87c51 mcs 51 chmos single-chip 8-bit microcontroller automotive y extended automotive temperature range ( b 40 cto a 125 c ambient) y high performance chmos process y power control modes y 4 kbyte on-chip rom/e prom y 128 x 8-bit ram y 32 programmable i/o lines y two 16-bit timer/counters y 5 interrupt sources y quick-pulse eprom programming y 2-level program memory lock eprom y boolean processor y programmable serial port y ttl- and cmos-compatible logic levels y 64k external program memory space y 64k external data memory space y idle and power down modes y once mode facilitates system testing y available in 12 mhz and 16 mhz versions y available in plcc and dip packages (see packaging specification, order y 231369) the mcs 51 chmos microcontroller products are fabricated on intel's reliable chmos process and are functionally compatible with the standard mcs 51 hmos microcontroller products. this technology combines the high speed and density characteristics of hmos with the low power attributes of chmos. this combina- tion expands the effectiveness of the powerful mcs 51 microcontroller architecture and instruction set. like the mcs 51 hmos microcontroller versions, the mcs 51 chmos microcontroller products have the following features: 4 kbytes of eprom/rom (87c51/80c51bh respectively); 128 bytes of ram; 32 i/o lines; two 16-bit timer/counters; a five-source two-level interrupt structure; a full duplex serial port; and on-chip oscillator and clock circuitry. in addition, the mcs 51 chmos microcontroller products exhibit low operating power, along with two software selectable modes of reduced activity for further power reductioneidle and power down. the idle mode freezes the cpu while allowing the ram, timer/counters, serial port, and interrupt system to continue functioning. the power down mode saves the ram contents but freezes the oscillator, causing all other chip functions to be inoperative. the 87c51 is the eprom version of the 80c51bh. it contains 4 kbytes of on-chip program memory that can be electrically programmed, and can be erased by exposure to ultraviolet light. the 87c51 eprom array uses a modified quick-pulse programming algorithm, by which the entire 4 kbyte array can be programmed in about 12 seconds. notice: this datasheet contains information on products in full production. specifications within this datasheet are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
automotive 80c31bh/80c51bh/87c51 270419 1 figure 1. mcs 51 microcontroller architectural block diagram 2
automotive 80c31bh/80c51bh/87c51 80c31bh/80c51bh/87c51 produc t options intel s extende d an d automotiv e temperatur e range product s ar e designe d t o mee t th e need s o f those application s whos e operatin g requirement s exceed commercia l standards. wit h th e extende d temperatur e rang e option , opera- tiona l characteristic s ar e guarantee d ove r th e tem- peratur e rang e of - 40 c to + 85 c ambient . fo r the automotiv e temperatur e rang e option , operational characteristic s ar e guarantee d ove r th e temperature rang e of - 40 c to + 125 c ambient. th e automotiv e an d extende d temperatur e versions o f th e mc s 5 1 microcontrolle r produc t familie s are availabl e wit h o r withou t burn-i n option s a s liste d in tabl e 1. a s show n i n figur e 2 . temperature , burn-in , and packag e option s ar e identifie d b y a one - o r two-letter prefi x t o th e par t number. 270419 C 2 * example: 80c51 indicates an automotive temperature range version of the 80c51 in a plcc package with 4 kbyte rom progra m memory. figure 2. mcs ? 51 microcontroller product family nomenclature table 1. temperature options temperature temperature operating burn-in classification designation temperature options c ambient extende d t - 4 0 to + 8 5 standard l - 4 0 to + 8 5 extended automotiv e a - 4 0 to + 12 5 standard b - 4 0 to + 12 5 extended 3 x x x x
automotive 80c31bh/80c51bh/87c51 diagrams are for pin reference only. package sizes are not to scale. 270419 3 pin (pdip) * eprom only ** do not connect reserved pins 270419 4 pad (plcc) figure 3. pin connections pin description v cc : supply voltage during normal, idle, and power down operations. v ss : circuit ground. v ss1 : v ss1 e(e prom plcc only) secondary ground. provided to reduce ground bounce and im- prove power supply bypassing. note: this pin is not a substitute for the v ss pin (pin 22). for rom and romless, pin 1 is reservededo not connect. port 0: port 0 is an 8-bit open drain bidirectional i/o port. as an output port each pin can sink 8 ls ttl inputs. port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external memory. in this application it uses strong internal pullups when emit- ting 1s. port 0 also receives the code bytes during eprom programming, and outputs the code bytes during program verification. external pullups are required during program verification. port 1 : port 1 is an 8-bit bidirectional i/o port with internal pullups. port 1 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (i il , on the datasheet) because of the inter- nal pullups. port 1 also receives the low-order address bytes during eprom programming and program verifica- tion. port 2 : port 2 is an 8-bit bidirectional i/o port with internal pullups. port 2 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (i il , on the data sheet) because of the inter- nal pullups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit address (movx @ dptr). in this application it uses strong internal pullups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ ri), port 2 emits the con- tents of the p2 special function register. port 2 also receives some control signals and the high-order address bits during eprom programming and program verification. port 3 : port 3 is an 8-bit bidirectional i/o port with internal pullups. port 3 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (i il , on the datasheet) because of the pull- ups. 4
automotive 80c31bh/80c51bh/87c51 port 3 also serves the functions of various special features of the mcs 51 microcontroller family, as listed below: pin name alternate function p3.0 rxd serial input line p3.1 txd serial output line p3.2 int0 external interrupt 0 p3.3 int1 external interrupt 1 p3.4 t0 timer 0 external input p3.5 t1 timer 1 external input p3.6 wr external data memory write strobe p3.7 rd external data memory read strobe port 3 also receives some control signals for eprom programming and program verification. reset: reset input. a logic high on this pin for two machine cycles while the oscillator is running resets the device. an internal pulldown resistor permits a power-on reset to be generated using only an exter- nal capacitor to v cc . ale/prog (eprom only) : address latch enable output signal for latching the low byte of the address during accesses to external memory. this pin is also the program pulse input (prog ) during eprom pro- gramming. in normal operation ale is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory. psen : program store enable is the read strobe to external program memory. when the 87c51/80c51bh is executing from internal program memory, psen is inactive (high). when the device is executing code from external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. ea /v pp : external access enable. ea must be strapped to v ss in order to enable the 87c51/80c51bh to fetch code from external pro- gram memory locations starting at 0000h up to 0ffffh. [ note, however, that if either of the lock bits is programmed, the logic level at ea is internally latched during reset. ] (eprom only.) ea must be strapped to v cc for internal program execution. v pp (eprom only) : this pin also receives the 12.75v programming supply voltage (v pp ) during eprom programming. 270419 5 figure 4. using the on-chip oscillator 270419 6 figure 5. external clock drive xtal1 : input to the inverting oscillator amplifier and input to the internal clock generating circuits. xtal2 : output from the inverting oscillator amplifi- er. oscillator characteristics xtal1 and xtal2 are the input and output, respec- tively, of an inverting amplifier which can be config- ured for use as an on-chip oscillator, as shown in figure 4. to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left uncon- nected, as shown in figure 5. there are no require- ments on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data- sheet must be observed. idle mode in idle mode, the cpu puts itself to sleep while all the on-chip peripherals remain active. the mode is invoked by software. the content of the on-chip ram and all the special functions registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hard- ware reset. it should be noted that when idle is terminated by a hardware reset, the device normally resumes pro- gram execution, from where it left off, up to two ma- chine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to 5
automotive 80c31bh/80c51bh/87c51 table 2. status of the external pins during idle and power down mode program ale psen port0 port1 port2 port3 memory idle internal 1 1 data data data data idle external 1 1 float data address data power down internal 0 0 data data data data power down external 0 0 float data data data note: for more detailed information on the reduced power modes refer to current embedded applications handbook, and applica- tion note ap-252, ``designing with the 80c51bh.'' internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle is terminat- ed by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. power down mode in the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. the on-chip ram and special function registers retain their values until the power down mode is terminated. the only exit from power down is a hardware reset. reset redefines the sfrs but does not change the on-chip ram. the reset should not be activated be- fore v cc is restored to its normal operating level and must be held active long enough to allow the oscilla- tor to restart and stabilize. design considerations # at power on, the voltage on v cc and rst must come up at the same time for a proper start-up. # before entering the power down mode the con- tents of the carry bit and b.7 must be equal. # when the idle mode is terminated by a hardware reset, the device normally resumes program exe- cution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to inter- nal ram in this event, but access to the port pins in not inhibited. to eliminate the possibility of an unexpected write when idle is terminated by re- set, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. # an external oscillator may encounter as much as a 100 pf load at xtal1 when it starts up. this is due to interaction between the amplifier and its feedback capacitance. once the external signal meets the v il and v ih specifications the capaci- tance will not exceed 20 pf. # for eprom versions exposure to light when the device is in operation may cause logic errors. for this reason, it is suggested that an opaque label be placed over the window when the die is ex- posed to ambient light. 6
automotive 80c31bh/80c51bh/87c51 program memory lock (eprom only) the 87c51 contains two program memory lock schemes: encrypted verify and lock bits. encrypted verify: the 87c51 implements a 32- byte eprom array that can be programmed by the customer, and which can then be used to encrypt the program code bytes during eprom verification. the eprom verification procedure is performed as usual, except that each code byte comes out logical- ly x-nored with one of the 32 key bytes. the key bytes are gone through in sequence. therefore, to read the rom code, one has to know the 32 key bytes in their proper sequence. lock bits : also on the chip are two lock bits which can be left unprogrammed (u) or can be pro- grammed (p) to obtain the following additional fea- tures: bit 1 bit 2 additional features u u none pu # externally fetched code can not access internal program memory. # further programming disabled. u p (reserved for future definition.) pp # externally fetched code can not access internal program memory. # further programming disabled. # program verification is disabled. when lock bit 1 is programmed, the logic level at the ea pin is sampled and latched during reset. if the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. it is necessary that the latched value of ea be in agreement with the current logic level at that pin in order for the device to func- tion properly. once mode the once (``on-circuit emulation'') mode facilitates testing and debugging of systems using the 87c51 without the 87c51 having to be removed from the circuit. the once mode is invoked by: 1. pull ale low while the device is in reset and psen is high; 2. hold ale low as rst is deactivated. while the device is in once mode, the port 0 pins go into a float state, and the other port pins and ale and psen are weakly pulled high. the oscillator cir- cuit remains active. while the 87c51 is in this mode, an emulator or test cpu can be used to drive the circuit. normal operation is restored when a normal reset is applied. 7
automotive 80c31bh/80c51bh/87c51 absolute maximum ratings * ambient temperature under bias b 40 cto a 125 c storage temperature .................... b 65 cto a 150 c voltage on ea /v pp pin to v ss ............... 0v to a 13.0v voltage on any other pin to v ss ......... b 0.5v to a 6.5v i ol per i/o pin ..................................................15 ma power dissipation ...............................................1.5w (based on package heat transfer limitations, not de- vice power consumption). typical junction temperature (t j ).................+135c (based upon ambient temperature at a 125 c) typical thermal resistance junction-to-ambient ( i ja ): pdip ........................................................75c/w plcc........................................................46c/w notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. dc characteristics : (t a eb 40 cto a 125 c; v cc e 5v g 10% (5v g 20% eprom only); v ss e 0v) symbol parameter min typ(1) max unit test (87c51/80c51bh) conditions v il input low voltage (except ea ) b 0.5 0.2 v cc b 0.25 v v il1 input low voltage to ea 0 0.2 v cc b 0.45 v v ih input high voltage (except xtal1, rst) 0.2v cc a 1.0 v cc a 0.5 v v ih1 input high voltage (xtal1, rst) 0.7 v cc a 0.1 v cc a 0.5 v v ol output low voltage (ports 1, 2, 3) 0.45 (7) vi ol e 1.6 ma (2) v ol1 output low voltage (port 0, ale, psen ) 0.45 (7) vi ol e 3.2 ma (2) v oh output high voltage 2.4 v i oh eb 60 m a (ports 1, 2, 3, ale, psen ) 0.9 v cc vi oh eb 10 m a v oh1 output high voltage (port 0 in 2.4 v i oh eb 800 m a external bus mode) 0.9 v cc vi oh eb 80 m a (3) i il logical 0 input current (ports 1, 2, 3) b 75 m av in e 0.45 v i tl logical 1-to-0 transition current b 750 m a (4) (ports 1, 2, 3) i li input leakage current (port 0) g 10 m av in e v il or v ih i cc power supply current: active mode @ 12 mhz (5) 11.5 25/20 ma idle mode @ 12 mhz (5) 1.3 6/5 ma (6) power down mode 3 100/75 m av cc e 2.2v to 5.5v rrst internal reset pulldown resistor 50 300 k x cio pin capacitance 10 pf notes: 1. ``typicals'' are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. the values listed are at room temp, 5v. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1- to-0 transitions during bus operations. in the worst cases (capacitive loading l 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9 v cc specification when the address bits are stabilizing. 8
automotive 80c31bh/80c51bh/87c51 notes: (continued) 4. pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. 5. iccmax at other frequencies is given by: active mode: 87c51 iccmax e 0.94 c freq a 13.71 80cx1bh iccmax e 1.47 c freq a 2.36 idle mode: iccmax e 0.14 c freq a 3.81 where freq is the external oscillator frequency in mhz. iccmax is given in ma. see figure 6. 6. see figures 7 through 10 for i cc test conditions. minimum v cc for power down is 2.0v. 7. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port port 0: 26 ma ports 1, 2, and 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 270419 7 figure 6. i cc vs. freq. valid only within frequency specifications of the device under test . 270419 8 figure 7. i cc test condition, active mode. all other pins are disconnected. 270419 10 figure 8. i cc test condition, idle mode. all other pins are disconnected. 270419 11 figure 9. i cc test condition, power down mode. all other pins are disconnected. 270419 9 figure 10. clock signal waveform for i cc tests in active and idle modes. t clch e t chcl e 5 ns. 9
automotive 80c31bh/80c51bh/87c51 explanation of the ac symbols each timing symbol has 5 characters. the first char- acter is always a `t' (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. a:address. c:clock. d:input data. h:logic level high. i:instruction (program memory contents). l:logic level low, or ale. p:psen . q:output data. r:rd signal. t:time. v:valid. w:wr signal. x:no longer a valid logic level. z:float. for example, t avll e time from address valid to ale low. t llpl e time from ale low to psen low. ac characteristics : (t a eb 40 cto a 125 c; v cc e 5v g 10% (5v g 20% eprom only); v ss e 0v; load capacitance for port 0, ale, and psen e 100 pf; load capacitance for all other outputs e 80 pf) external program and data memory characteristic s symbol parameter 12 mhz osc variable oscillator units min max min max 1/t clcl oscillator frequency mhz 87c51/80c51bh/80c31bh 3.5 12 16 t lhll ale pulse width 127 2t clcl b 40 ns t avll address valid to ale low 28 t clcl b 55 ns t llax address hold after ale low 48 t clcl b 35 ns t lliv ale low to valid instr in 224 4t clcl b 110 ns t llpl ale low to psen low 43 t clcl b 40 ns t plph psen pulse width 205 3t clcl b 45 ns t pliv psen low to valid instr in 135 3t clcl b 115 ns t pxix input instr hold after psen 00 n s t pxiz input instr float after psen 59 t clcl b 25 ns t aviv address valid to valid instr in 312 5t clcl b 105 ns t plaz psen low to address float 10 10 ns t rlrh rd pulse width 400 6t clcl b 100 ns t wlwh wr pulse width 400 6t clcl b 100 ns t rldv rd low to valid data in 252 5t clcl b 165 ns t rhdx data hold after rd high 0 0 ns t rhdz data float after rd high 97 2t clcl b 70 ns t lldv ale low to valid data in 517 8t clcl b 150 ns t avdv address valid to valid data in 585 9t clcl b 165 ns t llwl ale low to rd or wr low 200 300 3t clcl b 50 3t clcl a 50 ns t avwl address valid to rd or wr low 203 4t clcl b 130 ns t qvwx data valid to wr transition 23 t clcl b 60 ns t whqx data hold after wr high 33 t clcl b 50 ns t rlaz rd low to address float 0 0 ns t whlh rd or wr high to ale high 43 123 t clcl b 40 t clcl a 40 ns 10
automotive 80c31bh/80c51bh/87c51 external program memory read cycle 270419 12 external data memory read cycle 270419 13 external data memory write cycle 270419 14 11
automotive 80c31bh/80c51bh/87c51 external clock drive symbol parameter min max units 1/t clcl oscillator frequency 3.5 12 mhz 3.5 16 t chcx high time 20 ns t clcx low time 20 ns t clch rise time 20 ns t chcl fall time 20 ns external clock drive waveform 270419 17 serial port timingeshift register mode 12 mhz variable symbol parameter oscillator oscillator units min max min max t xlxl serial port clock cycle time 1.0 12t clcl m s t qvxh output data setup to clock rising edge 700 10t clcl b 133 ns t xhqx output data hold after clock rising edge 50 2t clcl b 117 ns t xhdx input data hold after clock rising edge 0 0 ns t xhdv clock rising edge to input data valid 700 10t clcl b 133 ns shift register mode timing waveforms 270419 15 ac testing input, output waveforms 270419 16 ac inputs during testing are driven at v cc b 0.5 for a logic ``1'' and 0.45v for a logic ``0.'' timing measurements are made at v ih min for a logic ``1'' and v il max for a logic ``0''. float waveforms 270419 18 for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh t g 20 ma. 12
automotive 80c31bh/80c51bh/87c51 eprom characteristics (eprom only) the 87c51 is programmed by a modified quick- pulse programming algorithm. it differs from older methods in the value used for v pp (programming supply voltage) and in the width and number of the ale/prog pulses. the 87c51 contains two signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes identify the device as an 87c51 manufactured by intel. table 3 shows the logic levels for reading the signa- ture byte, and for programming the program memo- ry, the encryption table, and the lock bits. the cir- cuit configuration and waveforms for quick-pulse programming are shown in figures 11 and 12. fig- ure 13 shows the circuit configuration for normal program memory verification. table 3. eprom programming modes mode rst psen ale/ ea / p2.7 p2.6 p3.7 p3.6 prog v pp read signature 1 0 1 1 0 0 0 0 program code data 1 0 0 * v pp 1011 verify code data 1 0 1 1 0 0 1 1 pgm encryption table 1 0 0 * v pp 1010 pgm lock bit 1 1 0 0 * v pp 1111 pgm lock bit 2 1 0 0 * v pp 1100 notes: ``1'' e valid high for that pin ``0'' e valid low for that pin v pp e 12.75v g 0.25v v cc e 5v g 20% during programming and verification * ale/prog receives 25 programming pulses while v pp is held at 12.75v. each programming pulse is low for 100 m s ( g 10 m s) and high for a minimum of 10 m s. 270419 19 figure 11. programming configuration 13
automotive 80c31bh/80c51bh/87c51 270419 20 figure 12. prog waveforms quick-pulse programming (eprom only) the setup for microcontroller quick-pulse program- ming is shown in figure 11. note that the 87c51 is running with a 4 to 6 mhz oscillator. the reason the oscillator needs to be running is that the device is executing internal address and program data trans- fers. the address of the eprom location to be pro- grammed is applied to ports 1 and 2, as shown in figure 11. the code byte to be programmed into that location is applied to port 0. rst, psen , and pins of ports 2 and 3 specified in table 3 are held at the ``program code data'' levels indicated in table 2. then ale/prog is pulsed low 25 times as shown in figure 12. to program the encryption table, repeat the 25- pulse programming sequence for addresses 0 through 1fh, using the ``pgmencryption table'' lev- els. don't forget that after the encryption table is programmed, verify cycles will produce only encrypt- ed data. to program the lock bits, repeat the 25-pulse pro- gramming sequence using the ``pgm lock bit'' lev- els. after one lock bit is programmed, further pro- gramming of the code memory and encryption ta- ble is disabled. however, the other lock bit can still be programmed. note that the ea /v pp pin must not be allowed to go above the maximum specified v pp level for any amount of time. even a narrow glitch above that volt- age level can cause permanent damage to the de- vice. the v pp source should be well regulated and free of glitches and overshoot. 270419 21 figure 13. program verification 14
automotive 80c31bh/80c51bh/87c51 program verification (eprom only) if lock bit 2 has not been programmed, the on-chip program memory can be read out for program verifi- cation. the address of the program memory location to be read is applied to ports 1 and 2 as shown in figure 13. the other pins are held at the ``verify code data'' levels indicated in table 3. the con- tents of the addressed location will be emitted on port 0. external pullups are required on port 0 for this operation. detailed timing specifications are shown in later sections of this datasheet. if the encryption table has been programmed, the data presented at port 0 will be the exclusive nor of the program byte with one of the encryption bytes. the user will have to know the encryption table contents in order to correctly decode the verification data. the encryption table itself can not be read out. reading the signature bytes (eprom only) the signature bytes are read by the same procedure as a normal verification of locations 030h and 031h, except that p3.6 and p3.7 need to be pulled to a logic low. the values returned are: (030h) e 89h indicates manufactured by intel (031h) e 57h indicates 87c51 program/verify algorithms (eprom only) any algorithm in agreement with the conditions list- ed in table 3, and which satisfies the timing specifi- cations, is suitable. erasure characteristics (eprom only) erasure of the eprom begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an ex- tended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadver- tent erasure. if an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. the recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrat- ed dose of at least 15 w-sec/cm 2 . exposing the eprom to an ultraviolet lamp of 12,000 m w/cm 2 rating for 30 minutes, at a distance of about 1 inch, should be sufficient. erasure leaves the array in an all 1s state. eprom programming and verification characteristics: (t a e 21 cto27 c, v cc e 5v g 20%, v ss e 0v) symbol parameter min max units v pp programming supply voltage 12.5 13.0 v i pp programming supply current 50 ma 1/t clcl oscillator frequency 4 6 mhz t avgl address setup to prog low 48t clcl t ghax address hold after prog 48t clcl t dvgl data setup to prog low 48t clcl t ghdx data hold after prog 48t clcl t ehsh p2.7 (enable ) high to v pp 48t clcl t shgl v pp setup to prog low 10 m s t ghsl v pp hold after prog 10 m s t glgh prog width 90 110 m s t avqv address to data valid 48t clcl t elqv enable low to data valid 48t clcl t ehqz data float after enable 0 48t clcl t ghgl prog high to prog low 10 m s 15
automotive 80c31bh/80c51bh/87c51 e p r o m programming and verification waveforms 27041 9 22 * fo r programmin g condition s se e figur e 11. fo r verificatio n condition s se e figur e 13. datasheet revision summary th e followin g ar e th e ke y difference s betwee n the -007 datashee t an d the -006 version: 1 . th e ``preliminary' ' statu s wa s remove d an d replace d wit h productio n statu s (n o label). 2 . trademar k wa s updated. th e followin g ar e th e ke y difference s betwee n th e -00 5 an d th e -00 6 versio n o f th e datasheet: 1 . preliminar y notic e adde d t o titl e page. 2 . figur e 3 pi n connection s th e nc ** pin s ar e no w reserved ** pins. 3 . figur e 3 pi n connection s rs t pi n i s no w rese t pin. 4 . rs t pi n descriptio n i s no w rese t pi n description. 5 . figur e 4 th e capacito r value s hav e bee n removed. 6 . cerdi p par t referenc e i n th e d.c . characteristic s sectio n ha s bee n removed. 7 . i cc ma x characteristic s hav e bee n correcte d t o reflec t tes t progra m conditions. 8 . t aviv an d t rldv formula s change d t o correlat e 1 2 mh z timings. th e followin g ar e th e ke y difference s betwee n th e -00 4 an d th e -00 5 versio n o f thi s datasheet: 1 . remove d reference s t o burn-i n option s i n tabl e 1 an d adde d explanatio n o f burn-i n offered . removed reference s t o commercia l temperatures. 2 . delete d referenc e t o `` = 1' ' designatio n 1 6 mhz. 3 . differentiate d v cc fo r rom/romles s an d e p r om. th e followin g ar e th e ke y difference s betwee n th e -00 2 an d th e -00 3 versio n o f thi s datasheet: 1 . change d th e titl e t o 80c31bh/80c51bh/87c5 1 chmo s single-chi p 8-bi t microcontroller. 2 . adde d th e pi n coun t fo r eac h packag e versio n i n figur e 2. 3 . remove d reference s t o burn-i n option s i n tabl e 1. 4 . adde d externa l oscillato r start-u p desig n considerations. th e followin g ar e th e ke y difference s betwee n th e -00 2 an d th e -00 1 versio n o f th e 80c51b h datasheet: 1 . maximu m i ol pe r i/ o pi n added. 2 . not e 7 o n maximu m curren t specification s adde d t o d c characterstics. 3 . datashee t revisio n summar y added. 16 th e followin g are the key differences between this datasheet and the -007 version: 1 . product prefix variables are now indicated with an x.

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